Analog fault diagnosis : a fault clustering approach

A novel analog circuit fault diagnosis method is proposed. This method uses a neural network paradigm to cluster different faults. It is capable of dealing with the common fault models in analog circuits, namely the catastrophic and parametric faults. The proposed technique is independent of the linearity or nonlinearity of the circuit. The process parameter drifts and component tolerance effects of the circuit are well taken care of. Several fault diagnosis strategies for different problem complexities are described. The proposed methodology is illustrated by means of an operational transconductance amplifier (OTA) exampl

Filter tuning system using fuzzy logic

The authors describe an expert system approach for tuning filters using fuzzy logic. The proposed system adjusts the filter components in order to meet the given window specifications. The system is described and experimental results are presented for a lowpass filter implemented with OTA

An analog integrated circuit design laboratory

We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a laboratory manual with analog circuit design theory, pre-laboratory exercises and circuit design specifications; a reference web page with step by step instructions and examples; the use of mathematical tools for automation and analysis; and state of the art CAD design tools in use by industry. Upon completion of the course, the students have skills for an entry level analog designer position

Very linear Ramp-generators for high resolution ADC BIST and calibration

Abstract-Two very linear ramp-generator designs are presented. The circuits are to be used in high-resolution ADC built-in-self-test (BIST) and on-chip calibration. The first design is to charge a capacitor by a small current, which is linear enough to test 14-bit ADCs. The second design is in a relaxation oscillator architecture. It is linear enough to test up to 12-bit ADCs. The two designs have been fabricated in CMOS 2um and 1.2um processes separately. I

A modular T-mode design approach for analog neural network hardware implementations

A modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a modular bidirectional associative memory network. The authors show that the size of the whole system can be increased by interconnecting more modular chips. It is also shown that by changing the interconnection strategy different neural network systems can be implemented, such as a Hopfield network, a winner-take-all network, a simplified ART1 network, or a constrained optimization network. Experimentally measured results from CMOS 2-μm double-metal, double-polysilicon prototypes (MOSIS) are presented.Peer Reviewe